Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic elements (CLEs) accessed from off-chip via programmable input/output blocks (IOBs). The CLEs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The interconnect structure, CLEs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLEs, IOBs, and interconnect structure are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The interconnect structure typically includes a large number of routing resources such as interconnect lines (e.g., metal wires) running generally horizontally and vertically between the various logic blocks, and programmable interconnect points (PIPs) that selectively couple the interconnect lines to each other and to input and output pins of the logic blocks. Interconnect lines within the CLE array can span, for example, one CLE, two CLEs, six CLEs, half of the chip, and so forth. By enabling selected PIPs, two signals in two logic blocks can be interconnected via one or more of the interconnect lines.
In order to test a PLD, typically every logic block, every interconnect line, and every PIP must be tested. This exhaustive testing process is required because, being a programmable device, the manufacturer cannot predict which of the literally millions of resources will be used by a customer's design. For some PLDs, the process of testing every resource on the device can be so time-consuming that testing becomes the largest expense in producing the PLD—larger than the cost of fabricating the die. Therefore, it is desirable to reduce PLD testing time as much as possible.
PLD providers typically offer a “family” of PLD products, that is, a set of PLDs that are closely related but include different numbers of similar logic blocks. A rectangular area (i.e., a “tile”) is designed and laid out that includes, for example, a CLE and the associated routing resources. The CLE can include, for example, one or more lookup tables and one or more memory elements paired with the lookup tables. The routing resources can include, for example, interconnect lines that connect by abutment with interconnect lines in adjacent tiles. The routing resources also include PIPs that allow signals access to and from the interconnect lines and CLEs.
Typically, a single tile is designed (e.g., including a CLE and the associated routing) and this single tile is used in the CLE arrays of all members of a PLD family. For example, the smallest member of a PLD family can include an 8×8 array of tiles, while the largest member of the same family can include a 128×120 array of the same tiles. Each of these tiles is similar, i.e., has the same number of resources located in about the same positions within the tile, although minor variations can occur in edge tiles, for example, to improve the layout area of the PLD or for other reasons. The number of interconnect resources provided within the tile is typically sized to accommodate the number of signals required by the largest array of tiles.
It is well known that the required number of interconnect resources grows at a rate larger than the number of tiles. Therefore, for example, if N interconnect lines per tile are sufficient to route a typical design in an 8×8 array, many more than N interconnect lines per tile are required to route a typical design in a 128×120 array. Similarly, for example, if M interconnect lines per tile are sufficient to route 90% of user designs in the 128×120 array, probably all user designs will route quickly within the smaller array having M interconnect lines per tile. Large numbers of interconnect lines and PIPs typically go unused in the smaller arrays.
A similar condition applies at the edges of each array, and particularly at the corners, regardless of the size of the array. Because of the uniformity of the tiles, the same number of interconnect lines per tile are available at the outer edges of the array as in the center of the array. However, signals are typically much more congested in the center of the array. Therefore, large numbers of interconnect lines and PIPs typically go unused in the outer tiles, and especially in the edge tiles.
Further, certain types of interconnect lines and PIPs are always unused in edge tiles, such as those used to connect directly to an adjacent tile that is not present because the edge of the array has been reached. Other types of interconnect lines and PIPs are very rarely used at the edges of an array, such as those generally used to route signals long distances in the direction of the edge.
Using similar tiles (and especially using uniform tiles) in the design of PLDs reduces the PLD design time, increases product yield due to the uniformity of the circuit structure, simplifies the implementation software for the PLD, and allows for many consistent timing specifications across the PLD family. However, this uniformity of design also leads to uniformity of testing.
In other words, each tile in the smaller members of the PLD family is typically tested just as exhaustively as tiles in larger members of the same PLD family, and each tile at the edges of the tile array is equally exhaustively tested.
Testing time for PLDs is an important issue not only in larger PLDs, but also in smaller PLDs, which typically include excessive routing resources and in which a larger percentage of the tiles are edge tiles and corner tiles. Therefore, it is desirable to reduce testing time for all PLDs in which arrays of similar tiles are used.